1. Technical Field of the Invention
The present invention relates to interconnect systems including a driver, interconnect, and receiver.
2. Background Art
Point-to-point on-chip interconnects between and within Functional Unit Blocks (FUBs) in semiconductor chips have evolved with integration as major on-chip performance and power bottlenecks. This is primarily because interconnect capacitance per unit length, dominated by sidewall fringing and cross-coupling, may increase hyperbolically with lateral dimension scaling and hence scale slower than does gate capacitance.
Mixed voltage swing based techniques have been studied for high performance/low power on-chip datapath interconnects. In mixed voltage swings techniques, the interconnects are driven at a reduced voltage swing, offering significant dynamic power and driver delay reduction. Mixed-swing techniques include those involving fully-differential interconnects. For example, FIG. 1 illustrates an interconnect system 10 including a driver 12 and a receiver 14. A single ended digital signal X having a swing between Vgnd and Vdd1 is received by driver 12. Signal X is converted by driver 12 into reduced swing signals Y and Y* on interconnects 20A and 20B (where Y* is the complement of Y). The resistance and capacitance of the interconnect is represented schematically by a resistor R and a capacitor C. Both signals Y and Y* have a swing of between Vgnd and Vdd2, where Vdd2 less than Vdd1. Signals Y and Y* are received by receiver 14 and converted therein back to a single ended signal Z have a full swing of between Vgnd and Vdd1 and which follows signal X or is its complement. Some prior art interconnect systems include an enable signal.
Noise immunity would be decreased by lowering the signal swing, however, the fully-differential interconnect technique helps improve noise immunity through common mode noise rejection. Further, fully differential receivers can avoid static power consumption during swing restoration. However, such approaches entail approximately a 2X penalty in interconnect layout area and effective switched capacitance per cycle due to their fully differential nature. Therefore, power reduction achieved due to the reduced swing is offset by the power penalty paid in driving the 2X high switched capacitance.
Accordingly, there is a need for an interconnect system that reduces power consumption and/or interconnect area.
In some embodiments, the invention includes an interconnect system having a single ended driver and a single ended hysteretic receiver. A single ended interconnect is coupled between the single ended driver and single ended receiver.
In other embodiments, the invention involves an interconnect system including interconnects, single ended drivers, and single ended hysteretic receivers connected to respective ones of the interconnects. The single ended drivers receive respective data-in signals and an enable signal and wherein the drivers transmit interconnect signals on the interconnects when the enable signal is asserted.
In yet other embodiments, the invention includes an interconnect system having interconnects, quasi-static drivers and receivers connected to respective ones of the interconnects. The quasi-static drivers to transmit interconnect signals on the interconnects, the quasi-static drivers receives a clock signal and respective data-in signals, and wherein the interconnect signals are pre-discharge when the clock signal changes from a first to a second state, and wherein when the clock signal is in the first state, the interconnect signals are related to the data-in signals.
In still other embodiments, the invention includes a pseudo differential interconnect system and an interconnect system with a dual rail driver.